1. Field of the Invention
This invention relates to superscalar microprocessors and more particularly to the predecoding of variable byte-length computer instructions within high performance and high frequency superscalar microprocessors.
2. Description of the Related Art
Superscalar microprocessors are capable of attaining performance characteristics which surpass those of conventional scalar processors by allowing the concurrent execution of multiple instructions. Due to the widespread acceptance of the x86 family of microprocessors, efforts have been undertaken by microprocessor manufacturers to develop superscalar microprocessors which execute x86 instructions. Such superscalar microprocessors achieve relatively high performance characteristics while advantageously maintaining backwards compatibility with the vast amount of existing software developed for previous microprocessor generations such as the 8086, 80286, 80386, and 80486.
The x86 instruction set is relatively complex and is characterized by a plurality of variable byte-length instructions. A generic format illustrative of the x86 instruction set is shown in FIG. 1A. As illustrated in the figure, an x86 instruction consists of from one to five optional prefix bytes 4, followed by an operation code (opcode) field 5, an optional addressing mode (Mod R/M) byte 6, an optional scale-index-base (SIB) byte 7, an optional displacement field 8, and an optional immediate data field 9.
The opcode field 5 defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field 5 follows the prefix bytes 4, if any, and may be one or two bytes in length. The addressing mode (MODRM) byte 6 specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte 7 is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation, and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field 8, which may be from one to four bytes in length. The displacement field 8 contains a constant used in address calculations. The optional immediate field 9, which may also be from one to four bytes in length, contains a constant used as an instruction operand.
Referring now to FIG. 1B, several different variable byte-length x86 instruction formats are shown. The shortest x86 instruction is only one byte long, and comprises a single opcode byte as shown in format (a). For certain instructions, the byte containing the opcode field also contains a register field as shown in formats (b), (c) and (e). Format (j) shows an instruction with two opcode bytes. An optional MODRM byte follows opcode bytes in formats (d), (f), (h), and (j). Immediate data follows opcode bytes in formats (e), (g), (i), and (k), and follows a MODRM byte in formats (f) and (h). FIG. 1C illustrates several possible addressing mode formats (a)-(h). Formats (c), (d), (e), (g), and (h) contain MODRM bytes with offset (i.e., displacement) information. An SIB byte is used in formats (f), (g), and (h).
The definitions of the encodings for the MOD and R/M fields of the MODRM byte are different depending upon whether the processor is operating in 16-bit mode or 32-bit mode. The definitions of the encodings for these fields for each mode are illustrated in FIGS. 1D-1G.
Considering the foregoing, it can readily be surmised that the complexity of the x86 instruction set poses difficulties in implementing high performance x86 compatible superscalar microprocessors. One difficulty arises from the fact that instructions must be aligned with respect to the parallel-coupled instruction decoders of such processors before proper decode can be effectuated. In contrast to most RISC instruction formats, since the x86 instruction set consists of variable byte-length instructions, the start bytes of successive instructions within a line are not necessarily equally spaced, and the number of instructions per line is not fixed. As a result, employment of simple, fixed-length shifting logic cannot in itself solve the problem of instruction alignment.
A further difficulty arises from the fact that certain instructions include scale-index-base calculations for calculating an offset address from the segment address. These calculations, including certain encodings in 16-bit mode, require the addition of three values to determine the offset which accordingly requires a relatively large amount of time for processing. This can limit the speed at which the processor can operate.
Superscalar microprocessors have been proposed that employ instruction predecoding techniques to help solve the problem of quickly aligning, decoding and executing a plurality of variable byte-length instructions in parallel. Improved predecoding techniques are desirable, however, that allow pipeline stages within a processor to be implemented with a relatively small number of cascaded levels of logic gates to thus support high frequency, high performance operations.